The present invention relates to programmable logic integrated circuits with an embedded processor. More specifically, the present invention relates to input/output (I/O) circuitry that is shared between a processor portion and a programmable logic portion of the integrated circuit.
Previously known integrated circuits (or chips) such as field programmable gate arrays (FPGAs) and programmable logic devices (PLDs) have provided I/O (input/output) pins that provide external access to circuits on the chip. Certain integrated circuits may require a large number of I/O pins on the chip to provide support to the internal circuitry and to provide the desired functionality and versatility. I/O pins and associated circuitry can take up a significant amount of room on the chip. Furthermore, integrated circuit technology continues to advance, and it is possible and desirable to provide more functionality on an integrated circuit. More I/O pins are generally needed to access or otherwise accommodate the additional on-chip functionality.
As an increasing number of I/O pins are required to be placed on a chip, chips must be made larger to accommodate the additional I/O pins. It may be undesirable to use chips with large surface areas in certain applications in which board space is limited. Also, packages that house chips typically accommodate a fixed number of I/O pins. There may be only a limited number of package sizes (e.g., 100 pins, 250 pins, 500 pins, and so forth). These may be xe2x80x9cstandardxe2x80x9d available package sizes. Therefore, when a chip exceeds the maximum number of I/O pins that a particular package size can accommodate, the chip must be housed in the next larger package size. This can significantly increase the cost of manufacturing the chip.
Therefore, there is a need for circuitry and methods that reduce or limit the number of I/O pins on a programmable logic chip.
The present invention is a programmable logic integrated circuit having a programmable logic portion and an embedded processor portion. The programmable logic and embedded processor portions are coupled together so data from one portion may be transferred to the other portion and visa versa. The programmable logic integrated circuit includes I/O pins that are shared by programmable logic and embedded processor portions of the integrated circuit. The embedded processor portion comprises a processor and associated logic and memory circuits. The programmable logic and embedded processor portions can access data signals from and send data signals to the shared I/O pins. The input and output data signals are multiplexed to control access to the shared I/O pins. The multiplexers may be controlled by control signals that determine when particular I/O pins are accessed by the programmable logic portion or the embedded processor portion of the integrated circuit.
By providing shared I/O pins and associated circuitry, the number of additional I/O pins that are required on an integrated circuit with programmable logic and embedded processor portions is limited. The shared I/O circuitry of the present invention also limits the increase in size of a chip when an embedded processor portion is combined with a programmable logic portion on an integrated circuit. The shared I/O circuitry may limit the number of additional pins and chip size enough so that the integrated circuit does not have to be placed in a larger package size.
The circuitry associated with the shared I/O pins on the integrated circuit may be configured to a different I/O standard depending upon whether the I/O pins are accessed by the programmable logic portion or by the embedded processor portion. Control signals that determine an I/O standard are multiplexed by the shared I/O circuitry of the present invention. Input data signals received at the shared I/O pins that are transmitted to the embedded processor portion may be monitored by circuitry within the programmable logic portion to provide debugging features, system wake-up features, etc.